CS 3443: Computer Systems

Fall 2005 Syllabus [PDF][Doc]

Instructor:

Dr. Xiaolin (Andy) Li
Office: Tulsa NH 328 (918-5948188), Stillwater MSCS 223 (405-744-2338)
Office Hours: W 2:30pm -4:30pm before the class or by appointment
Email: xiaolin @ cs
URL: http://www.cs.okstate.edu/~xiaolin

TA:

Ravikumar Nidadavolu

Office: Stillwater MSCS 222                     

Office Hours: Tuesday 2pm-4pm or by appointment

Email: ravikun @ cs.okstate.edu

Class Meeting Time and Place:

Time: Wednesday 4:30pm-7:10pm (First class starts on 8/24)

Place: Tulsa NCB 211, Stillwater MSCS 310

Course Objective and Description:

This course will focus on fundamental principles of computer architecture, and functional and register level description of computer systems and structures. It will cover instruction set, addressing techniques, linkage, assembly language, computer arithmetic, datapath and control, pipelining, memory hierarchy, and input/output operations.

Prerequisite:

CS 2113 (Computer Science I) and some basic C/Unix knowledge.

Required Textbook: 

Computer Organization & Design, the Hardware/Software Interface, 3rd Edition, Patterson and Hennessy, Morgan Kaufman, 2004, ISBN: 1558606041.

Other references: 

n

VHDL Starter’s Guide, 2nd Ed., Yalamanchili, 2005

Computer Architecture: A Quantitative Approach, 3rd Ed., Hennessy and Patterson, 2002

Course Homepage:

http://www.cs.okstate.edu/~xiaolin/teaching/cs3443

Course Outline (tentative):

  1. Introduction
  2. Data Representation
    • Binary numbers
    • Conversion to/from binary, octal, hexadecimal
    • Floating point representation
  3. Instruction Set Architecture (ISA)
    • Bridge between software and the processor (CPU)
    • Accumulator
    • Stack
    • General purpose registers
    • Load/store
  4. MIPS ISA
    • Assembler
    • Pseudo instructions
    • System calls
    • Procedure calls
    • SPIM, other ISAs
  5. Performance Evaluation
  6. (Midterm I)
  7. Basics of Logic Design
    • Boolean functions
    • Logic gates
    • Multiplexers
    • Adder
    • Arithmetic logic unit (ALU)
  8. Designing a Processor: datapath and control
    • Single cycle datapath
    • Single cycle control
    • Multicycle datapath implementation
  9. (Midterm II)
  10. Pipelining
    • Introduction to pipelining
    • A pipelined datapath
    • Pipelined control
    • Data hazards and branch hazards
  11. Memory Hierarchy
    • Cache
    • Virtual memory
  12. InputOutput
  13. Multiprocessor
  14. Final Exam

Grading Policies:

Class participation bonus: 5% (attendance is not required and attendance without participation = 0)

Incentive bonus for significant improvement (show me your progress and ask for extra points (max. 10%) )

Programming and homework assignments and quiz: 30%

Midterm Exams (2): 20% each (Time: TBA)

Final Exam (Comprehensive): 30% (Time: TBA)

Attachments:

  • OSU Syllabus Attachment, Spring 2005

            http://osu.okstate.edu/acadaffr/syllabusattachment.htm