CS 3443: Computer Systems

Announcements:

The course homepage is at http://cs.okstate.edu/~xiaolin/teaching/cs3443/. But we will mainly use the Blackboard system (http://blackboard.okstate.edu/) for announcements, homework, grades, course documents/slides, and submitting your homework/project assignments.

Fall 2006 Syllabus

Instructor:

Dr. Xiaolin (Andy) Li
Office: 223 MSCS (Stillwater, 405-744-2338), 328 NH (Tulsa, 918-5948188)
Office Hours: W 4pm-6pm (onsite) (M 4pm-5pm, or by appointment)
Email: xiaolin @ cs
URL: http://www.cs.okstate.edu/~xiaolin

Teaching Assistant:

Huanyu Zhao
Office: 204 MSCS (Stillwater)
Office Hours: M 3:00PM-5:00PM or by appointment
Email: huanyu @ cs.okstate.edu

Class Meeting Time and Place:

Time: 7:20pm-10:00pm, Wednesday (The first class starts on 8/23, Stillwater)
Place: Stillwater CLB 106A, Tulsa NCB 226

Course Objective and Description:

This course will focus on fundamental principles of computer architecture, and functional and register level description of computer systems and structures. It will cover instruction set, addressing techniques, linkage, assembly language, computer arithmetic, datapath and control, pipelining, memory hierarchy, and input/output operations.

Prerequisite:

CS 2113 (Computer Science I) and some basic C/Unix knowledge.

Required Textbook:

Computer Organization & Design, the Hardware/Software Interface, 3rd Edition, Patterson and Hennessy, Morgan Kaufman, 2004, ISBN: 1558606041.

Other References:

Embedded System Design: A Unified Hardware/Software Introduction, Frank Vahid and Tony Givargis, Wiley, 2002.
Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog, 3rd Edition, Springer, 2005.
VHDL Starter's Guide, Yalamanchili, Sudhankar, Prentice-Hall, 1998.

Course Homepage:

http://www.cs.okstate.edu/~xiaolin/teaching/cs3443

Course Outline (tentative):

Introduction
Instruction Set Architecture (ISA)

Bridge between software and the processor (CPU)
Accumulator
Stack
General purpose registers
Load/store

Data Representation

Binary numbers
Conversion to/from binary, octal, hexadecimal
Floating point representation

MIPS ISA

Assembler
Pseudo instructions
System calls
Procedure calls
SPIM, other ISAs
(Midterm I)

Performance Evaluation
Basics of Logic Design

Boolean functions
Logic gates
Multiplexers
Adder
Introduction to Verilog
Arithmetic logic unit (ALU)

Designing a Processor: datapath and control

Single cycle datapath
Single cycle control
Multicycle datapath implementation
(Midterm II)

Pipelining

Introduction to pipelining
A pipelined datapath
Pipelined control
Data hazards and branch hazards

Memory Hierarchy

Cache
Virtual memory

InputOutput
Multiprocessor
Final Exam

Grading Policies:

Class participation bonus: 5%
Programming and homework assignments, and quiz: 30%
Midterm Exams (2): 20% each (Time: TBA)
Final Exam (Comprehensive): 30% (Time: TBA)

OSU Syllabus Attachment, Fall 2006

http://osu.okstate.edu/acadaffr/aa/syllabusattachment-Fall.htm

Interesting Links

Textbook Home Page
SPIM Tutorial (spim, spimwin)
SPIM Home Page
Verilog Simulators
VHDL Simulators: VHDL Simili, ActiveHDL

WWW Collection of Computer Architecture

CPU Info Center

Online classic textbooks: Computer structures: readings and examples by C. Gordon Bell and Allen Newell. New York, McGraw-Hill [c1971] , 2nd edition Computer structures: principles and examples by Siewiorek, D., C. G. Bell, and A. Newell, New York, McGraw-Hill [c1982]

comp.arch google group

Association for Computing Machinery (ACM) and Special Interest Group on Computer Architecture (SIGARCH)